/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_CPPIDMA_RX_FLOW_CONFIG_H_
#define CSLR_CPPIDMA_RX_FLOW_CONFIG_H_

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for RX_FLOW_CONFIG
**************************************************************************/
typedef struct {
    volatile Uint32 RX_FLOW_CONFIG_REG_A;
    volatile Uint32 RX_FLOW_CONFIG_REG_B;
    volatile Uint32 RX_FLOW_CONFIG_REG_C;
    volatile Uint32 RX_FLOW_CONFIG_REG_D;
    volatile Uint32 RX_FLOW_CONFIG_REG_E;
    volatile Uint32 RX_FLOW_CONFIG_REG_F;
    volatile Uint32 RX_FLOW_CONFIG_REG_G;
    volatile Uint32 RX_FLOW_CONFIG_REG_H;
} CSL_Cppidma_rx_flow_configRx_flow_configRegs;


/**************************************************************************
* Register Overlay Structure
**************************************************************************/
typedef struct {
    CSL_Cppidma_rx_flow_configRx_flow_configRegs	RX_FLOW_CONFIG[129];
} CSL_Cppidma_rx_flow_configRegs;




/**************************************************************************
* Register Macros
**************************************************************************/

/* RX_FLOW_CONFIG_REG_A */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A(n)      (0x0U + ((n) * (0x20U)))

/* RX_FLOW_CONFIG_REG_B */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B(n)      (0x4U + ((n) * (0x20U)))

/* RX_FLOW_CONFIG_REG_C */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C(n)      (0x8U + ((n) * (0x20U)))

/* RX_FLOW_CONFIG_REG_D */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D(n)      (0xCU + ((n) * (0x20U)))

/* RX_FLOW_CONFIG_REG_E */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E(n)      (0x10U + ((n) * (0x20U)))

/* RX_FLOW_CONFIG_REG_F */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F(n)      (0x14U + ((n) * (0x20U)))

/* RX_FLOW_CONFIG_REG_G */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G(n)      (0x18U + ((n) * (0x20U)))

/* RX_FLOW_CONFIG_REG_H */
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H(n)      (0x1CU + ((n) * (0x20U)))


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* RX_FLOW_CONFIG_REG_A */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_MASK  (0x00000FFFU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_MASK  (0x00003000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_SHIFT  (12U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_MASK  (0x01FF0000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_MAX  (0x000001ffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_MASK  (0x02000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_SHIFT  (25U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_MAX  (0x00000001U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_MASK  (0x0C000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_SHIFT  (26U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_MASK  (0x10000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_SHIFT  (28U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_MAX  (0x00000001U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_MASK  (0x20000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_SHIFT  (29U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_MAX  (0x00000001U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_MASK  (0x40000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_SHIFT  (30U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_MAX  (0x00000001U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RESETVAL  (0x00000000U)

/* RX_FLOW_CONFIG_REG_B */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_MASK  (0x000000FFU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_MAX  (0x000000ffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_MASK  (0x0000FF00U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_SHIFT  (8U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_MAX  (0x000000ffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_MASK  (0x00FF0000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_MAX  (0x000000ffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_MASK  (0xFF000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_SHIFT  (24U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_MAX  (0x000000ffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RESETVAL  (0x00000000U)

/* RX_FLOW_CONFIG_REG_C */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_MASK  (0x0000000FU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_MAX  (0x0000000fU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_MASK  (0x00070000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_MAX  (0x00000007U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_MASK  (0x00700000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_SHIFT  (20U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_MAX  (0x00000007U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_MASK  (0x07000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_SHIFT  (24U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_MAX  (0x00000007U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_MASK  (0x70000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_SHIFT  (28U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_MAX  (0x00000007U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RESETVAL  (0x00000000U)

/* RX_FLOW_CONFIG_REG_D */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_MASK  (0x00000FFFU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_MASK  (0x00003000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_SHIFT  (12U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_MASK  (0x0FFF0000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_MASK  (0x30000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_SHIFT  (28U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RESETVAL  (0x00000000U)

/* RX_FLOW_CONFIG_REG_E */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_MASK  (0x00000FFFU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_MASK  (0x00003000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_SHIFT  (12U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_MASK  (0x0FFF0000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_MASK  (0x30000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_SHIFT  (28U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RESETVAL  (0x00000000U)

/* RX_FLOW_CONFIG_REG_F */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_MASK  (0x0000FFFFU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_MAX  (0x0000ffffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_MASK  (0xFFFF0000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_MAX  (0x0000ffffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RESETVAL  (0x00000000U)

/* RX_FLOW_CONFIG_REG_G */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_MASK  (0x00000FFFU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_MASK  (0x00003000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_SHIFT  (12U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_MASK  (0xFFFF0000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_MAX  (0x0000ffffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RESETVAL  (0x00000000U)

/* RX_FLOW_CONFIG_REG_H */

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_MASK  (0x00000FFFU)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_SHIFT  (0U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_MASK  (0x00003000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_SHIFT  (12U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_MASK  (0x0FFF0000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_SHIFT  (16U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_MAX  (0x00000fffU)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_MASK  (0x30000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_SHIFT  (28U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_RESETVAL  (0x00000000U)
#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_MAX  (0x00000003U)

#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RESETVAL  (0x00000000U)

#ifdef __cplusplus
}
#endif
#endif
